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PCI Subsystem:
• PCI-X: The PCI-X
specification, an extension of the PCI 2.2 specification, was driven by
the growing need for I/O bandwidth. The PCI 2.2 specification provides a
maximum throughput of 528 MB/s of shared bandwidth on a given bus. With
new I/O technologies, such as Gigabit Ethernet, Gigabit Fibre Channel
and multi-channel Ultra320 SCSI, the 528 MB/s
bandwidth of PCI 2.2 is fast becoming a constraint in servers.
The PCI-X specification supports a 64-bit
bus operating at speeds of 66 MHz,
100 MHz and
133 MHz, providing throughput speeds
of 528 MB/s, 800 MB/s
and 1064 MB/s respectively. PCI-X also supports hot-swap and is
fully backward compatible to PCI 2.2 devices. Be aware that, as is the
case with PCI 2.2, the PCI-X bus operates at the frequency of the lowest
frequency card connected to the bus.
- A PCI-X bus operating at 66 MHz can
support up to four devices.
- A PCI-X bus operating at 100 MHz can
support a maximum of two devices
- A PCI-X bus operating at 133 MHz can
support only a single device.
• PCI Hot-plug (PHP): is the ability
to add or replace a PCI adapter card while the system is running. This
provides increased availability because the system doesn’t need to be
powered down to replace a failed card. Hot-plug types include:
- Hot
replace: The process of removing an adapter card and then inserting
an identical adapter into the same slot. The replacement adapter card
will use the same PCI resources that were assigned to the previous card,
and its driver does not need to be updated. Sometimes referred to as
"Like-for-Like Replacement."
- Hot
add: The process of inserting an adapter card into a previously
unoccupied slot. This operation requires a driver for the added adapter
and a reserved PCI resource by the system BIOS. Sometimes referred to as
hot expansion.
- Hot
upgrade: The process of removing an adapter card and inserting an
upgraded adapter that requires different PCI resources than the original
card. The adapter’s driver may or may not use the same driver as the
previous adapter.
Notes:
1.
The Intel Quad Xeon MP Server system
SPSH4 (ASI
SKU: 17382) and SRSH4 (ASI
SKU: 17249) support
the above hot-plug PCI types, but not all operating systems do.
2. To support PCI hot-plug, systems
require hot-plug hardware, a hot-plug compatible operating system, and
hot-plug capable adapter drivers. To ensure backward compatibility, a
combination of hot-plug and conventional versions of each of these
components is permitted, including mixing both hot-plug and conventional
adapter drivers. If a conventional driver is loaded under a hot-plug
capable operating system, or a hot-plug driver is loaded under a
conventional operating system, the driver has the capability it always
had in the conventional environment.
Memory Subsystem:
• Single-bit
error correction: If a
single-bit error is detected, the ECC logic generates a new
"recovered" 64-bit QWord with a pattern that corresponds to the originally received
8-bit ECC parity code. The corrected data is returned to the requestor,
most likely the processor or a PCI master.
• Multi-bit error
detection: Additional
errors within the same QWord constitute a multi-bit error, which maybe unrecoverable. In the case of a multi-bit memory error, a non-maskable
interrupt (NMI) is issued that instructs the system to shut down to avoid data corruption. Multi-bit errors are
very rare.
• Memory
scrubbing:
Error correction is performed on data being read from memory. The
correction is then passed to the requestor and at the same time the error is
"scrubbed" or corrected in main memory. Memory scrubbing prevents the accumulation of single-bit errors in main memory that
would then become unrecoverable multi-bit errors.
• "Chipkill":
Chipkill is the ability of the memory system to withstand a multi-bit
failure within a DRAM device, including a failure that causes incorrect data on all data bits of
the device. When "x4" memory is installed the ECC function can
detect and correct a four-bit error caused by a single failed memory
chip and the system continues to function, though system performance
will be affected. When "x8" memory is installed the ECC
function will detect an eight-bit error caused by a single failed memory
chip but will not be able to correct the error. In this situation a
fatal error will be issued.
• Memory Interleaving (2-Way
& 4-Way): Memory Interleaving
is an advanced technique used by high-end server motherboards and
chipsets to improve memory performance. Memory interleaving increases
bandwidth by allowing simultaneous access to more than one chunk of
memory. Interleaving works by dividing the system memory into multiple
blocks. This improves performance because the processor can transfer
more information to/from memory in the same amount of time, and helps
alleviate the processor-memory bottleneck that is a major limiting
factor in overall performance. This design
requires that DIMMs operate in pairs (2-way) or quads (4-way), where a
pair consists of two specific DIMM sockets to provide the aggregate
144-bit wide memory data path, and where a quad consists of four
specific DIMM sockets to provide the aggregate 288-bit wide memory data
path. Each block of memory is
accessed using different sets of control lines, which are merged
together on the memory bus. When a read or write has begun to one block,
a read or write to other blocks can be overlapped with the first one.
The more blocks, the more that overlapping can be done.
Note:
Current server chipsets that support all of the above memory features
are the Intel E7500, & Serverworks
GC-HE & GC-LE.
Storage Subsystem:
• SAF-TE: Stands for "SCSI
accessed fault-tolerant enclosure" and is a processor found
on intelligent hot-swap drive bays and backplanes. The backplane is an
embedded application subsystem that responds to SAF-TE messages
transmitted through the SCSI bus, monitors fan speeds and backplane
temperature, and reports a warning or critical error if outside of
defined thresholds. The SAF-TE processor monitors the backplane and
notifies the RAID controller (if present) when a drive has been inserted
or removed. The major objective here is auto hot-plug, which allows a
defective drive to be easily removed from the subsystem and a
replacement unit installed.
•
Zero-channel
RAID:
To use this function, one PCI slot on the motherboard must be specially
wired for RAID I/O Steering (RAIDIOS). The RAID adapter is dependent on
the baseboard’s SCSI controller to transfer data to the system’s
storage devices. RAIDIOS has two components. The first is IRQ steering,
which re-routes the IRQs of the onboard SCSI controller. The second is
the initialization device select (IDSEL) signal, which allows the ZCR
controller to take control of the SCSI device. The ability to control
the IDSEL signal is what allows this newer version of zero-channel RAID
to be Windows Hardware Quality Labs (WHQL) certified. ASI
carries Adaptec and Intel based Zero-Channel RAID cards.
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